For a memory controller interfacing with a memory via one or more memory channels and having a shared error correction code (ECC) decoder, data received from the memory to the memory controller is queued up prior to being decoded by the decoder and then corrected for any errors in the received data. The queue in such traditional memory controllers has to be large enough to store data from the one or more memory channels reading data from the memory. The decoder coupled to the queue that receives the data, via the queue from the memory, determines the parity associated with the data and identifies any error in the data received from the memory. The data is then transmitted from the memory controller to the processor for processing after the error in the data is corrected based on the parity error.
The queue and the decoder hardware of the memory controller is one of the timing bottlenecks limiting fast error correction of data received from memory. The queue and the decoder hardware also take up a large silicon area to handle the large amount of data i.e., to decode and identify errors in the data from the memory.